IJE TRANSACTIONS B: Applications Vol. 31, No. 2 (February 2018) 292-298   

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G. Rajesh Kumar and K. Babulu
( Received: August 04, 2016 – Accepted in Revised Form: November 30, 2017 )

Abstract    Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes more amount of power. Test circuitry is intensively used for memory testing. This may cause excessive power consumption during memory testing. Sophisticated and efficient techniques with less overhead on power must be needed. Regarding memories, power consumption is very much high during testing when compared with normal functional mode. March test algorithms are popular testing techniques used for memory testing. Power consumption during testing can be reduced by reducing the switching activity in test circuitry. A new test technique is proposed in this paper to reduce power consumption in test mode by reducing the switching activity in Built in Self-Test circuitry. Address sequencing in the address decoder is changed in such a way that it reduces switching activity.


Keywords    Built in Self-Test (BIST), Low Power Test, March Test Algorithm, Memory Built in Self-Test (MBIST), Memory Testing


چکیده    حافظه در ساخت سیستمهای دیجیتال نقش مهمی را ایفاد می نمایند. همچنانکه مدارهای حافظه در حال رشد اند آزمون و تست مدار نیز باید رشد نماید. متد موثر با توان پائین و سرعت بالا مورد نیاز می باشد. حافظه های خود-آزما برای تست حافظه پیشنهاد شده است. مدارهای سری و مدارهای ترکیبی برای آزمون حافظه توان زیادی مصرف می نمایند. آزمون مدار برای آزمون حافظه استفاده می شود. این امر موجب مصرف بی رویه توان شده است. روشهای موثر و پیچیده با توان مصرف پائین نیازمند است. هنگام آزمون مدار حافظه در حالت عادی مصرف توان بالاست. الگوریتم آزمون مارس روش آزمون متداولی است که برای تست حافظه توان مصرفی را می تواند کاهش داد و فعالیت تست مدار را نیز بخوبی انجام دهد. روش نوین ارائه شده در این مقاله توان مصرفی برای آزمون مدار حافظه را کاهش داده بعلاوه ترتیب کد و تعویض مدار به طریقی است که موجب کاهش مصرف توان می گردد


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