Abstract




 
   

IJE TRANSACTIONS C: Aspects Vol. 32, No. 3 (March 2019) 381-392   

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  REVERSIBLE LOGIC MULTIPLIERS: NOVEL LOW-COST PARITY-PRESERVING DESIGNS
 
F. Eslami-Chalandar, M. Valinataj and H. Jazayeri
 
( Received: April 05, 2018 – Accepted in Revised Form: March 07, 2019 )
 
 

Abstract    Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are proposed with the parity-preserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’s algorithm and its enhanced version called the K-algorithm, utilizing the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be utilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed multipliers are much better than the existing designs regarding the main criterions used in reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.

 

Keywords    Reversible Logic; Parity-Preserving Gates; Multiplication; Booth’s Algorithm; Error Detection; Fault-Tolerance

 

چکیده   

منطق برگشت‌پذیر یکی از نمونه‌های نوظهور برای بهینه‌سازی توان مصرفی است که می‌تواند به جای مدارهای فعلی مورد استفاده قرار گیرد. همچنین، تحمل‌پذیری اِشکال به صورت تشخیص یا تصحیح خطا جنبه‌ای ضروری برای سیستم‌های پردازشی امروزی است. در این مقاله، به خاطر اهمیت عملیات ضرب در سیستم‌های محاسباتی، چندین طراحی جدید برای ضرب‌کننده برگشت‌پذیر با ویژگی حفظ پریتی پیشنهاد می‌شوند که برای تشخیص خطا مناسب خواهند بود. در ابتدا، دو ضرب‌کننده سری علامت‌دار بهینه بر مبنای الگوریتم بوث و نسخه بهبودیافته آن به نام الگوریتم K، با استفاده از چینش‌هایی جدید برای گیت‌های برگشت ‌پذیر ارائه می‌گردند. سپس، ضرب‌کننده سری کم‌هزینه دیگری بر پایه روش مرسوم جمع- انتقال پیشنهاد می‌شود که برای کاربردهایی شامل ضرب اعداد بدون علامت مناسب است. در انتها، یک ضرب‌کننده موازی علامت‌دار جدید بر پایه روش باو-وولی پیشنهاد می‌گردد که برای کاربردهای نیازمند به سرعت بالا مناسب است. نتایج مقایسه‌ها نشان می‌دهد که ضرب‌کننده‌های پیشنهادی با توجه به معیارهای اصلی مورد استفاده در مدارهای با منطق برگشت‌پذیر شامل هزینه کوانتومی، تعداد گیت، تعداد ورودی‌های ثابت و تعداد خروجی‌های بی‌استفاده، بسیار بهتر از طراحی‌های موجود هستند.

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