Abstract




 
   

IJE TRANSACTIONS C: Aspects Vol. 31, No. 9 (September 2018) 1194-1202    Article in Press

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  LDO BASED NOISE MINIMIZATION OF ACTIVE MODE POWER GATED CIRCUIT
 
D. Nath and S. Pradhan
 
( Received: March 10, 2016 – Accepted: April 01, 2018 )
 
 

Abstract    Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode and noise is analyzed. The effect of different noise minimization approaches for reducing power supply noise is evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage regulator is proposed in this paper. The amount of charge in the internal nodes of the power gating circuit passes through the sleep transistors during the wake-up transition is controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed newly in such a way that can be used to reduce bounce noise by minimizing voltage fluctuation on the power rail of power gating circuit. Architectures have been developed in Synopsys Custom Designer tool at iPDK 90nm technology. Percentage saving of noise on the power supply is reduced up to 99%.

 

Keywords    architecture powergating data-retention leakage noise low-dropout voltage

 

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