Abstract




 
   

IJE TRANSACTIONS A: Basics Vol. 28, No. 4 (April 2015) 546-552   

PDF URL: http://www.ije.ir/Vol28/No4/A/8-1924.pdf  
downloaded Downloaded: 149   viewed Viewed: 1883

  ANALYSIS OF INTEGRAL NONLINEARITY IN RADIX-4 PIPELINED ANALOG-TO-DIGITAL CONVERTERS
 
E. Farshidi and N. Rahmani
 
( Received: August 25, 2013 – Accepted: January 29, 2015 )
 
 

Abstract    In this paper an analytic approach to estimate the nonlinearity of radix-4 pipelined analog-to-digital converters due to the circuit non-idealities is presented. Output voltage of each stage is modeled as sum of the ideal output voltage and non-ideal output voltage (error voltage), in which non-ideal output voltage is created by capacitor mismatch, comparator offset, input offset, and finite gain of amplifier. The integral nonlinearity (INL) can be obtained as the expected value of total input error due to the errors in all stages of radix-4 pipelined ADC.

 

Keywords    radix-4, pipeline, capacitor mismatch, total error, integral nonlinearity(INL).

 

چکیده    در این مقاله یک روش تحلیلی برای تقریب میزان غیرخطی بودن مبدلهای آنالوگ به دیجیتال ناشی از اثرات غیر ایدال مداری ارائه شده است. ولتاژ خروجی هر طبقه بصورت جمع ولتاژ ایدال و ولتاژ غیرایدال(ولتاژ خطا) مدل شده است که در آن ولتاژ غیرایدال بدلیل ناهمسانی خازنها، افست مقایسه گر، افست ورودی و بهره محدود تقویت کننده ها ایجاد شده است. معیار تجمیع غیرخطی به عنوان معیار تقریب تاثیر همه خطاها از همه طبقات مبدلهای آنالوگ به دیجیتال پایه-4 بدست می آید.

References   

 

1.        S.H. Lewis, “Optimizing the stage resolution for pipelined multistage analog-to-digital converters for video rate applications,” IEEE Trans circuits and system II,Exp. Briefs, Vol. 39, No. 8, (1992), 516-523.

2.        D. Goren, E. Shamsaev, I.A. Wagner, “ A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC,” Proc. of  IEEE Design Automation Conference (DAC), (2001),127-132.

3.        P.J. Quinn, A.H.M. van Roermund, “ Accuracy Limitations of Pipelined ADCs,” Proc. of  IEEE Int. symp. circuits and systems, (2005).

4.        G. Nikandish, B. Sedighi, M. Sharif  Bakhtiar, “ INL Prediction Method in Pipeline ADCs,” APCCAS, (2006), 13-16.

5.        M. Furuta, S. Kawahito, D. Miyazaki, “ A Digital-Calibration Tehnique for Redundant Radix-4 Pipelined Analog-to-Digital Converters,” IEEE Trans, Vol. 56, (2007), 2031-2310.

6.        D.  W. Cline and P. R. Gray, “ A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 µm CMOS,” IEEE J. Solid- State Circuits, Vol. 31, (1996), 294-303.

7.        A. Avizienis,“Signed-digit number representations for fast parallel arithMetic,” IRE Trans. Electron. Computer, Vol. EC-10, (1961), 389-400.

8.        I. Ahmed, J. Mulder, and D. A. Johns, “A low-power capacitive charge pump based pipelined ADC,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 5, (2010), 1016-1027.

9.        K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, “A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 10, (2008), 2303-2310.

10.     F. Maloberti, Data converters, Springer, (2007).

11.     A. Panigada, I. Galton, “Digital Background Correction of Harmonic Distortion in Pipelined ADCs, IEEE Trans. Circuits and Systems I: Regular Papers,  Vol.53, No.9, (2007), 1885–1895.

12.     S. Yang, J. Cheng, P. Wang, “Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs,” Elsevier Microelectronics Journal, Vol.41, (2010), 403-410.

13.     C. Tsang, .Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, B. Nikolic, “Background ADC calibration in digital domain,” in Proc. IEEE Custom Integrated Circuits Conf. , (2008), 301–304.

14.     A. Meruva, B. Jalali, “Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs,” in proc. IEEE International Symposium on Circuits and Systems, , (2007), 1233–1236.

15.     S.J. Azhari and L. Safari, “Fully Differential Current Buffers Based on a Novel Common Mode Separation Technique,” International Journal of Engineering (IJE) Transactions B: Applications, Vol. 24 , No. 3, (2011), 237 – 249.

16.     E. Farshidi and A. Keramatzadeh, A New Approach for Low Voltage CMOS based on Current-controlled Conveyors,” International Journal of Engineering (IJE) Transactions B: Applications, Vol. 27 , No. 5, (2014), 723 – 730.

17.     M. Sasikumar and S. Chenthur Pandian   “Modified Bi-directional AC/DC Power Converter with Power Factor Correction,” International Journal of Engineering (IJE) Transactions B: Applications, Vol. 25 , No. 3, (2012), 175– 180.

18.     M. Fallah and H. MiarNaimi, “A Novel Low Voltage, Low Power and High Gain Operational Amplifier Using Negative Resistance and Self Cascode Transistors,” International Journal of Engineering (IJE) Transactions C: Aspects, Vol. 26 , No. 3, (2013), 303 – 308.

19.     M. D Nair and R. Sankaran, “Simulation and Experimental Verification of Closed Loop Operation of Buck / Boost DC-DC Converter with Soft Switching,” International Journal of Engineering (IJE) Transactions C: Aspects, Vol. 25 , No. 4, (2012), 267 – 274.

20.     Y. Kebbati, Modular approach for an ASIC integration of electrical drive controls,” International Journal of Engineering (IJE) Transactions B: Applications, Vol. 27 , No. 2, (2011), 107– 118.


Download PDF 



International Journal of Engineering
E-mail: office@ije.ir
Web Site: http://www.ije.ir